USB Pulse Generator – no longer available
Introduction
This project was developed as technology prover for a USB interfaced FPGA based test equipment. What I wanted from this exercise was a set of software and firmware routines for interfacing with the PC which could be re-used in future projects. The pulse generator was chosen because the external circuitry required is minimal, as all the hard work is done inside the FPGA.
Despite its humble back ground this design provides a feature rich pulse generator for a fraction of the price of a commercial
Capabilities Of the Pulse Generator
Outputs
The pulse generator has two pulse outputs. Both outputs are connected to an independent pulse generator capable of outputting pulses from 105ns to 50s with 21ns resolution. The pulse generator can operate as a single shot monostable or as a free running astable oscillator.
Inputs
The pulse generator has one input which is shared between the two channels. The input is used as a Gate signal for a channel in astable mode or as a pulse trigger for a channel in monostable mode. Also the PC software can generate a software based trigger.
Example scope trace
Linked Mode
In this mode the two channels are linked together in a master slave arrangement. Cahnnel two is always in monostabel mode , whilst channel one may be in either Astable or monostable. the output of channel 1 is used to trigger chanel 2, this way there is always a fixed relationship between the two channels. The delay from channel 1 to channel may be skewed under program control.
Burst operation
Each output can generate a burst of pulses, up to 255. In this case the the pulses are output with a 1:1 mark space ratio.
Jitter operation
Using this mode a programmable amount of jitter is added to each edge of the output pulse. The jitter can range from 21ns to 1ms.
| MODE | Min Pulse (ns) | Max Pulse (s) | Resolution (ns) | Min Freq (Hz) | Max Freq (MHz) | True/Inverted Gate | True/Inverted Output | True/Inverted Trigger | Re-Trigger | Burst Mode | Jitter Mode |
| ASTABLE | 110 | 50 | 21 | 0.02 | 10 | YES | YES | NA | NA | To 255 pulses | From 21ns to 1ms |
| MONOSTABLE | 110 | 50 | 21 | 0.02 | 10 | NA | NA | YES | YES | To 255 pulses | From 21ns to 1ms |
Design and Operation
Circuit Design
The whole design is based around The FTDI FT232RL USB interface and an Altera ACEX 50k gate FPGA. The design was laid out onto a 4 layer PCB which fits in to a nice small box which won’t take up much room on your workbench. Because of the level of integration available from the USB interface and the FPGA, the schematics are relatively simple. The whole project boils down to 3 ICs, 3 regulators plus a hand full of diodes, resistors and capacitors.
FPGA Coding
The FPGA is coded in VHDL using the Altera Quatrus WEB Edition toolset. The resulting code is then downloaded by the PC to the FPGA by the application software. This allows for a very fast debug cycle and easy field based updates.
PC Coding
The PC software for this project has been developed using Open Source products. I have used the wxwidgets visual library for the developing the user interface. This is a cross platform visual library and will hopefully allow the design to be ported to Linux at some stage. The Open Source community have developed a nice IDE and compiler set which can use the wxwidgets library, called wxDev-C++, which uses the Bloodshed Dev-C++ IDE.
Operation
The FPGA provides guts of the operation, the PC provides the user interface. The PC passes to the FPGA a set of operation values for each of the channels, the FPGA then takes these values and converts them into the timed pulses seen on the outputs. The USB data overhead is in the region of 64 bytes for each update of the pulse generator’s characteristics.
Before the FPGA can communicate to the PC it needs to be configured. To do this the USB device is put into a special BIT BANG IO mode, which allows the PC to use the pins as individual IO pins. during normal operation the USB interfaces communicates using RS232 protocols.
The FPGA is clocked from the USB interface at 48MHz – this sets the timing resolution to 20.83ns(21ns to an engineer).Internally the FPGA design is based on 32 bit counters, which sets the maximum pulse widths and frequencies. I have limited this in the GUI to be 50s.
The output stage uses a three gates of a 74ACT245 to provide the required current to drive a 50R load.
Project Files
Schematics In PDF Format
The gerbers are available here.
Quartus VHDL Project
DEv C++ Project files
